Patents

Granted Patents

Patent No.: US 9,768,113 B2 .​Yannick Feurprier, Joe Lee, Lars Liebmann, Yann Mignot, Terry Sooner, Douglas M. Tricket, M. Yilmaz. "Self Aligned Via in Integrated Circuit" (Date of Patent: Sep. 19, 2017)


Patent No.: US 9,385,078 B1.​Yannick Feurprier, Joe Lee, Lars Liebmann, Yann Mignot, Terry Sooner, Douglas M. Tricket, M. Yilmaz. "Self Aligned Via in Integrated Circuit" (Date of Patent: Jul. 5, 2016)


Patent No.: US 9,373,582 B1.​Yannick Feurprier, Joe Lee, Lars Liebmann, Yann Mignot, Terry Sooner, Douglas M. Tricket, M. Yilmaz. "Self Aligned Via in Integrated Circuit" (Date of Patent: Jun. 21, 2016)

Filed Patents

A.K. Okyay, N. Bıyıklı, K. Topallı, A. Haider, P. Deminskyi, H. Eren, M. Yilmaz. “A Method for Area Selective Atomic Layer Deposition and Thereof” (January 2017), Republic of Turkey Patent Institute, Application#: 2016/13505.


A. K. Okyay, N. Bıyıklı, K. Topallı, T. Khan, A. Haider, P. Deminskyi, H. Eren, M. Yilmaz. “A Method for Area Selective Atomic Layer Deposition and Thereof” (June 2016), Republic of Turkey Patent Institute, 2016/08790.